In data transmission, for example via two-wire lines which are normally in cable bundles, interferences may occur as a result of electrical couplings of other lines into the same cable bundle or else of other systems, such as, for example, television transmitters, radio transmitters or electrical appliances, which may lead to so-called bit errors. This means that a transmitted bit sequence is changed by the interference.
Various coding methods are used in order to be able to correct errors of this kind. In general in these coding methods redundant data are transmitted, such as, for example, check sums by which bit errors of this kind can be found and also corrected.
In ADSL (Asymmetric Digital Subscriber Line)—and VDSL (Very High Bit Rate Digital Subscriber Line)—systems the so-called Reed Solomon code is used, for example, for coding. The data to be transmitted are here combined into so-called code words with a length of up to 255 bytes, which comprise up to 16 bytes with redundant data, with the aid of which bit errors can be corrected in up to 8 bytes.
However, conditional on the type of data transmission, for example when using so-called trellis coding, or on short interferences of high intensity, bit errors sometimes occur in a short period of time on such a large scale that considerably more than 8 bytes in succession are changed or corrupted and thus correction is no longer possible by means of the coding.
A so-called interleaver is used to solve this problem. The interleaver distributes the transmission of a code word to be transmitted over a fairly long period of time and fills the gaps arising with preceding or following code words. For example, first a byte of a first code word, then a byte of a second code word and then a byte of a third code word are transmitted, before a byte of the first code word is transmitted again. In this way it is achieved that if there is interference only a few bytes of a single code word are affected and thus correction with the aid of the coding continues to be possible.
A transmission system operating on this principle is illustrated schematically in FIG. 4. Here a coder 1 which codes a signal a to be transmitted, for example according to the Reed Solomon coding, is provided on the side of a transmitting device 2. The thus coded signal b is nested by an interleaver device or an interleaver 46. The thus arising signal c is transmitted to a receiver 8 via a transmission line 6. In the receiver 8 a corresponding interleaver 47 undoes the nesting of the data, in order to generate a signal d, substantially corresponding to the coded signal b. This signal d is decoded by a decoder 9, in order to generate a decoded received signal e, corresponding to the signal a to be transmitted.
Naturally, both on the transmitter and the receiver side there is a multiplicity of further elements, such as filters, transmitting amplifiers, analog-to-digital or digital-to-analog converters or modulation devices. However, they are not essential for understanding the present invention and are therefore not illustrated in FIG. 4.
In ADSL or VDSL systems so-called convolutional interleavers are used as interleavers 46. The de-interleaver 47 is then correspondingly configured. The mode of operation of such convolutional interleavers or de-interleavers will be explained in greater detail below.
Interleavers of this kind are designed to nest blocks with a length of I bytes in each case with one another. A block of this kind either corresponds to one code word or each code word is divided into several blocks before nesting.
Each byte in a block is delayed corresponding to its position according to the following formula:V1=j·(D−1);j=0,1,2, . . . I−1  (1)V1 here designates the delay in clock units, one byte being transmitted per clock unit. j designates the position of the respective byte within the block and D designates the so-called depth of the interleaver, which essentially indicates over how many blocks the interlacing is performed.
In the receiver this process is undone again, in that again a delay is performed, this being byVd=(I−1−j)·(D−1);j=0,1,2, . . . I−1  (2)Vd here designates the delay in the de-interleaver.
Each byte is therefore delayed in total by Vj+Vd=(I−1)·(D−1) clock units, so that after the de-interleaver the original sequence is restored again. Appropriate intermediate storage is needed for this delay. The required memory for this is in each case (I−1)·(D−1)/2 bytes both in the interleaver and in the de-interleaver.
In FIG. 5 is an option for implementing an interleaver or de-interleaver of this kind by I delay paths in each case, implemented in the form of so-called FIFO buffers or FIFO memories (First In First Out).
Reference numeral 20 here designates a data block with I bytes, continuously numbered from 0 to I−1 and fed to the interleaver 46. As indicated by an arrow A, the individual bytes of block 20 are fed successively, i.e. clock by clock, to delaying devices 10-14, depending on their position, there being a total of I delaying devices of this kind.
Delaying device 10 to which the byte with the position “0” of block 20 is fed does not cause a delay in this case, so is substantially formed by a line. Delaying device 11 to which the byte with the position “1” of block 20 is fed is formed by a FIFO memory with (D−1)·1/I bytes. The depth D of the interleaver 46 is normally chosen for VDSL systems in such a way that D−1 is a multiple of I. In general this expression indicates an average memory size, which may vary, for example, in that the FIFO memory is also used as an output buffer. The FIFO memory operates in such a way that a byte written into it is output again after write/read cycles of the FIFO memory corresponding to (D−1)·1/I. As—according to arrow A—the FIFO memory of delaying device 11 is described only by each Ith byte and, as will be described below, is also read out only in each Ith clock, there is a resulting delay by D−1 clocks for delaying device 11.
The delay increases from delaying device to delaying device, so the FIFO memory of delaying device 13, to which byte no. I−2 is fed, has a memory capacity of (D−1)·(I−2)/I bytes and that of delaying device 14 a memory capacity of (D−1)·(I−1)/I bytes.
The bytes output by delaying devices 10 to 14 are transmitted sequentially via the transmission line 6 from FIG. 4, as indicated in FIG. 5 by a double changeover switch 48. On the side of the receiver the de-interleaver 47 likewise comprises delaying devices, designated in FIG. 5 by reference numerals 15 to 19. Delaying device 15 comprises a FIFO memory comprising (D−1)·(I−1)/I bytes and delaying device 16 comprises a FIFO memory with (D−1)·(I−2)/I bytes, until finally delaying device 19 does not cause a delay. Delaying devices 15 to 19 are configured as complementary to delaying devices 10 to 14 of the interleaver 46. The incoming data are distributed over delaying devices 15 to 19 in such a way that the data delayed by delaying device 10 on the transmitter side are fed to delaying device 15 and the data output by delaying device 11 are fed to delaying device 16, etc., until finally the data output by delaying device 14 are fed to delaying device 19, in other words are not delayed. As indicated by an arrow C, delaying devices 15 to 19 are read out sequentially, in order to form a data block 33 with I bytes again.
Because of the complementary configuration of delaying devices 10 to 14 and 15 to 19 each byte in the interleaver and de-interleaver is delayed in total by (I−1)·(D−1) bytes, so that after the de-interleaver 47 the bytes are in the original sequence of data again.
A scale for the quality of the combination of coding for the purposes of error correction and interleaver is the so-called “error protection length”, which indicates how many corrupted bytes in succession can be correctly restored. This depends on the one hand on the coding, in particular on the number of redundant bytes or data used, and also on the depth D of the interleaver.
In the set-up of a transmission connection a line quality is normally determined, for example by transmitting test data, and depending on this, on the one hand the transmission rate and on the other hand parameters of the above-described measures for avoiding transmission errors, in particular the code word length, the number of redundant bytes, the size of the block I and the interleaver depth D are set. These parameters must in this case be determined in such a way that on the one hand the necessary protection against byte errors and a required error protection length are achieved, but on the other hand a net data rate for the transmission is also maximised. The interleaver depth D is additionally limited by the available memory.
During transmission it is possible, though, that the type and strength of the source of the interferer may change. If interferences of the line become stronger this may lead to transmission errors. If interfering influences disappear, a possible achievable data rate is not utilised with the initially set parameters.
Conventionally, if sizeable bit errors have occurred over a specific period of time and they can no longer be corrected, the data transmission is completely stopped and then the connection is newly set up or the system reactivated, the above mentioned parameters of the coding and the interleaver being re-determined. By this measure the data transmission is interrupted for a relatively long time, which may be in the range of minutes. This interruption of the data transmission is very troublesome for many applications. Therefore regular adaptation to the current interference and associated optimisation of the transmission rate is not possible.
It is therefore desirable to be able to change at least part of the parameters mentioned during operation, without a noticeable interruption in the data transmission being associated with it.